This invention relates generally to computer memory, and more particularly to providing low latency constrained coding for parallel busses.
Significant impairments to signal integrity can occur on an electrical parallel bus when certain data patterns occur. For example, simultaneous switching of a large fraction of data inputs is a significant source of noise in a single-ended transmission bus. Reducing the number of transitions can reduce noise as well as have a positive effect on transmission power consumption.
The most well known solution for reducing the number of transitions is to add an additional signal pin to the bus. Then it is determined if more than half of the pins would switch if the pending data is sent through the bus. If more than half of the pins would switch, then the data is inverted and the additional pin is used to transmit information about the inversion. An advantage of this solution is that it is very simple. A disadvantage of this solution is the cost of the additional pin, which must be added to every bus on which the encoding will be applied.